Technical Field
The present disclosure generally relates to high speed integrated circuits, and in particular, to the fabrication of interconnect structures using a self-aligned dual damascene process.
Description of the Related Art
As integrated circuit technology advances, building metal interconnect structures that are used to wire transistors together becomes more and more challenging. Metal lines can assume a variety of different shapes, from straight wires to cells made up of intertwined C-shapes. Regardless of their shapes, design rules for metal lines are typically based on scaling a pitch dimension that assumes a regular pattern of equal line widths and spacings between the metal lines at each metal layer. Metal line widths are generally expected to shrink with every new process generation to further improve integrated circuit performance.
Depending on the type of process integration scheme used, vias connecting stacked metal lines vertically to one another are constrained to be smaller than the metal lines in order for the via footprint to be surrounded by metal. Such a constraint exists, for example, when forming vias according to a self-aligned dual damascene process that avoids a separate via lithography step. Thus, as the metal line design widths shrink with each process generation, the self-aligned vias shrink as well. However, smaller vias incur higher via resistance, causing RC delays to worsen. In addition, smaller via footprints cause the via aspect ratio, i.e., the ratio of height to width, to increase, making the vias taller and narrower, and therefore more difficult to fill with metal. Incomplete via fill in turn degrades reliability by causing open circuit failures, for example. Thus, for multiple reasons, it is advantageous for via footprints to remain large, while metal lines continue to shrink with each technology generation.